Computing devices rely on storage devices to store code and data used in the computing devices. Solid state memory devices provide nonvolatile storage without the mechanical parts used in conventional spinning disk storage devices. A common solid state storage technology is flash memory, and more specifically, NAND-based flash memory is particularly common. Solid state memory such as flash memory is written or programmed by applying a high voltage on the programmed wordline. A programmed cell lies at the intersection of the programmed wordline and selected bitline. An inhibited cell lies at the intersection of programmed wordline and unselected bitline. Cells that need to be programmed are held at a zero channel potential (by passing the voltage from the selected bitline to their channel) and those that do not need to be programmed are inhibited by boosting their channel (isolating them from the unselected bitline and allowing the channel to capacitively couple to the inhibit voltage). Inhibit voltage is applied on two or several adjacent wordlines to the programmed wordline. The boosted voltage of the inhibited channel can be referred to as boosted channel potential, and is typically higher than the normal operating voltage level at which data can be read from the memory device. The boosted channel potential of the inhibited channel is determined by the capacitive coupling from the inhibit voltage as well as the boost leakage in the channel.
Memory devices are susceptible to two different categories of program error, which are commonly referred to as “disturbs,” or unintentional programming or changing other memory cells that are not the intended target of a write operation. The memory cells could be referred to as victim cells. The two categories of unintentional programming can be identified as program disturb (PD) and inhibit disturb (ID). PD occurs on cells belonging to the programmed wordline and unselected bitline. ID occurs on cells belonging to the inhibited wordlines (wordlines under the inhibit voltage) and the selected bitline. PD occurs when boosted channel potential is insufficient (low) in the inhibited channel, which causes unintentional programming. Typically, the system increases the inhibit voltage on the inhibit wordlines to improve the boosted channel potential on the unselected bitline, which ultimately reduces PD.
In ID, cells on the inhibit wordlines that are also on a selected bitline can be unintentionally written during the program operation, especially with high inhibit voltages. Thus, increasing the inhibit voltage can reduce PD, but increasing the inhibit voltage tends to increase the ID. It will thus be understood that there is a tradeoff between providing a sufficiently high inhibit voltage to maintain PD at a desired rate, and not increasing the inhibit voltage to maintain ID at a desired rate.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.